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Huawei is accelerating its next-generation Ascend 960DT AI chip launch as it aims to challenge Nvidia and narrow China’s AI computing gap with the U.S.

Huawei now expects its next-generation Ascend 960DT AI chip to be ready in the first quarter of 2027, moving up from a previously planned third-quarter 2027 launch. The update was announced at Huawei Connect, with Huawei positioning the accelerated schedule as part of its effort to challenge Nvidia in AI computing.
For readers tracking AI infrastructure, the key takeaway is timing: Huawei is signaling urgency in both chip development and system-level AI hardware.
Huawei is also emphasizing its Peerium Computing Architecture, an approach designed to connect large numbers of AI chips into bigger computing systems. The architecture relies on UnifiedBus, Huawei’s technology for linking processors with memory, storage, and networking hardware.
Huawei says the Atlas 950 SuperPoD and SuperCluster are the first systems based on this architecture, and that an Atlas 950 SuperCluster can connect up to 256,000 accelerator cards. The systems are intended for both AI training and inference.
The announcement lands in a broader competition over AI computing capacity, with Huawei seeking to compete with Nvidia and close China’s AI computing gap with the U.S. It also comes ahead of a planned September 24 meeting in Washington, DC, between U.S. President Trump and Chinese President Xi Jinping.
Huawei’s progress comes despite U.S. restrictions on China’s access to advanced semiconductor technology. The strategic implication is clear: AI chip self-sufficiency remains a central priority for China’s tech sector.
The faster chip timeline raises questions about the scale of Huawei’s broader AI systems. China tech analyst Rui Ma noted that Huawei had previously described an Atlas 960 SuperPoD scaling to 15,488 Ascend 960 chips, while the latest announcement referred to a system with 4,096 chips.
That makes the next milestone about more than launch timing. Watch whether Huawei can translate earlier chip availability into larger, reliable AI computing systems that can support real-world training and inference workloads.

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